1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, an electrode connection structure in a semiconductor integrated circuit device.
2. Description of the Prior Art
A semiconductor integrated circuit device, in particular, one comprising a compound semiconductor such as gallium arsenide (GaAs), gallium arsenide/gallium aluminum arsenide (GaAs/GaAlAs), or indium phosphide (InP), often includes two or more types of electrodes of different materials interconnected with each other. For example, a metal semiconductor field effect transister (MES FET) using GaAs has gate electrodes of, e.g., aluminum (Al), which makes Schottky contact with GaAs of an active region, and source and drain electrodes of, e.g., gold-germanium (AuGe), which make ohmic contact with the GaAs of the active region. A GaAs integrated circuit (IC) which is integrated with such MES FET's requires electrical connections between the above two types of electrodes.
FIGS. 1 to 3 show an inverter circuit as an example of such connections. FIG. 1 is a circuit diagram of an inverter circuit, FIG. 2 is a plan view of the patterns for elements of the inverter circuit of FIG. 1, and FIG. 3 is a sectional view taken on the line III--III in FIG. 2. In the inverter circuit, a driver transistor Tr.sub.1, a load transistor Tr.sub.2, and a next stage driver transistor Tr.sub.3 are MES FET's. The gate of the load transistor Tr.sub.2 is connected to the source of the load transistor Tr.sub.2 as well as the drain of the driver transistor Tr.sub.1 and the gate of the next stage driver transistor Tr.sub.3. In the inverter circuit, the gate of the driver transistor Tr.sub.1 is an inlet terminal (IN). The drain of the load transistor Tr.sub.2 is connected to one side of a power source (V.sub.DD). The source of the driver transistor Tr.sub.2 is connected to the other side of the power source or ground (V.sub.SS).
Referring to FIGS. 2 and 3, in an insulating or semi-insulating GaAs substrate 1, active regions 2a and 2b exist as an N-type or N.sup.+ -type region on which gate electrodes 3a, 3b and 3c and drain or source electrodes 4a, 4b and 4c are formed. The metal of the gate electrodes 3a, 3b and 3c and the metal of the drain or source electrodes 4a, 4b and 4c are different and make Schottky contact and ohmic contact, respectively, with GaAs. All the electrodes 3a, 3b, 3c, 4a, 4b and 4c are covered with a silicon dioxide (SiO.sub.2) layer 5 (not shown in FIG. 2). On the SiO.sub.2 layer 5, interconnecting lines 6a and 6b, made of, e.g., titanium-platinum-gold (TiPtAu), are formed connecting the electrodes 4a and 4b through contact windows 7a and 7b, respectively. The Tr.sub.2 gate electrode 3b, Tr.sub.2 source and Tr.sub.1 drain electrode 4c, and Tr.sub.3 gate electrode 3c are connected by means of connecting portions 8a and 8b. Three through holes 7c, 9a, and 9b are opened in the SiO.sub.2 layer 5 above the connecting portions 8a and 8b and the electrode 4c. These connecting portions 8a and 8b and the electrode 4c are connected by interconnecting lines 6c, 10a, and 10b which are made of TiPtAu.
The reason for connecting the gate electrode 3b and the drain or source electrode 4c by means of the interconnecting lines 6c, 10a and 10b is that if the aluminum (Al) of the gate electrode and the gold-germanium (AuGe) of the drain or source electrode are directly connected to each other, the aluminum and the gold would react with each other to form purple plague, an intermetallic compound, lowering the yield and reliability of the semiconductor device. Thus, the gate electrodes 3b and 3c and the drain or source electrode 4c are connected by means of the interconnecting lines 6c, 10a and 10b, and the connections between, on the one hand, the interconnecting lines 6c, 10a and 10b and, on the other hand, the gate electrodes 3b and 3c, and the drain or source electrode 4c are made by means of through holes 7c, 9a and 9b. The connections may easily result in insufficient electrical contact between the interconnecting lines and the electrodes due to the presence of SiO.sub.2 residue in the through holes.
Further, connections made by means of through holes 9a and 9b require increased area for formation, since consideration must be given to tolerances in aligning the through holes 9a and 9b with the connecting portions 8a and 8b of the gate electrodes 3b and 3c, respectively, and in aligning the interconnecting lines 10a and 10b with the through holes 9a and 9b, respectively. This increased area for through hole connections lowers the degree of integration of a semiconductor integrated circuit device having the above-described inverter circuit.
Referring to FIGS. 2 and 3, due to considerations of alignment tolerances, the through holes 9a and 9b are formed in a square of 2 um (microns).times.2 um and the connecting portions 8a and 8b of the gate electrodes 3b and 3c are formed in a square of 6 um.times.6 um. The interconnecting lines 10a and 10b are formed so as to include a square of 4 um.times.4 um near the position of the through holes 9a, 9b. Further, the 2 um distance is taken between the connecting portions 8a and 8b of the gate electrodes 3b and 3c and the active region 2a and between the connecting portions 8a and 8b and the active region 2b. Therefore, a 10 um distance is needed between the active regions 2a and 2b.
The use of, for example, titanium-platinum-gold (TiPtAu) can be considered in place of aluminum as th gate-electrode metal so as to avoid the formation of the above-mentioned purple plague and to avoid the increased area of connection portions by means of interconnecting lines and through holes. The titanium-platinum-gold line as an extending portion of the gate electrodes can be formed directly on the source or drain electrode and make contact between them without the formation of purple plague. The direct connection between the two types of electrodes of different metals enables elimination of the use of the interconnecting lines as well as the connection by means of through holes between the interconnecting lines and the electrodes. Therefore, a decrease in the size necessary for making the connections between the two types of results, that is, the alignment tolerances of the layers at the through holes eliminated.
However, a titanium-platinum-gold electrode which makes Schottky contact with gallium arsenide cannot be formed before an ohmic contact is formed since the heat treatment necessary for making the ohmic contact has an adverse effect on the Schottky contact. Therefore, the titanium-platinum-gold line as mentioned above can be formed on the source or drain electrode only within the boundaries of the source or drain electrode. This reduces the reliability of the contact between them and lowers the yield of the semiconductor device due to possible disconnection at the step appearing at the edge of the source or drain electrode. Further, the titanium-platinum-gold (TiPtAu) gate electrode does not allow source and drain regions to be made using the gate electrode as a mask for ion implantation or diffusion since the gate electrode cannot be made before the ohmic contact for the source and drain electrodes. This requires alignment tolerances of the gate electrode with the source and drain regions, increasing the distance between the source and drain regions. This requirement also appears in the case of, e.g., aluminum gate electrodes (see Naoki Yokoyama's Japanese Patent Application No. 55-189544 filed on Dec. 30, 1980; U.S. patent application Ser. No. 334923 filed on Dec. 28, 1981; and European Patent Application No. 81306151.2 filed on Dec. 24, 1981).